1. Field of the Invention
The present invention relates to a method of using a semiconductor device. More particularly, the present invention relates to a method of using a non-volatile memory and a refresh method of a non-volatile memory, which are applied to a non-volatile memory that utilizes a charge-trapping layer for data storage.
2. Description of the Related Art
Recently, electrically erasable programmable read-only memory (E2PROM) and flash memory as members of non-volatile memory are widely used in various electronic products. Conventional E2RPOM and flash memory devices use floating gates (FG) to store charges, and therefore store merely one bit in each memory cell.
To increase the storage density of programmable non-volatile memory, a new type of non-volatile memory using charge-trapping layers to store N bits (N≧2) per cell is proposed. For example, U.S. Pat. No. 6,011,725 discloses a nitride read-only memory, which uses a nitride layer for trapping charges and is capable of storing two bits in each memory cell. Referring to FIG. 1A, an N-bit memory cell usually includes a charge trapping layer 120 between two dielectric layers 110 and 130, wherein the three layers 110–130 are between the substrate 100 and the gate 140.
An N-bit cell is usually written with channel hot electron injection (CHEI). When the channel current is from the source/drain (S/D) region 150 to the S/D region 160, hot electrons are produced in the channel region near the S/D region 150 and attracted to the corresponding portion of the above charge trapping layer 120 near the S/D region 150 by a high positive voltage applied to the gate 140. On the contrary, when the channel current is from 160 to 150, hot electrons are attracted to a portion of the charge trapping layer 120 near the S/D region 160. Accordingly, by altering the relative polarity between the two S/D regions 150 and 160 to switch the direction of the channel current, two bits can be written to a single N-bit cell.
Referring to FIG. 1B, an N-bit cell having been written through CHEI is usually erased by injecting holes to the storage sites containing electrons through band-to-band tunneling hot hole (BTBTHH) effect. If the two storage sites in one memory cell both contain electrons, the erase operation has to be conducted twice, i.e., from the left side and the right side respectively, to inject holes into the left storage site and the right storage site, respectively.
However, as CHEI is utilized to locally inject hot electrons, there is still a minor amount of hot electrons entering the middle portion of the charge trapping layer 120 and being trapped therein, as shown in FIG. 1A. Since no hole enters the middle portion of the charge trapping layer 120 in the erase operation utilizing BTBTHH effect, the electrons trapped therein will not be annihilated, as shown in FIG. 1B. Therefore, after a lot of such write/erase cycles, quite a few hard-to-erase electrons are accumulated in the middle portion, as shown in FIG. 1C. As a result, the erase-state (low-level) threshold voltage (Vt) of the memory cell is progressively raised with the number of write/erase cycles, so that the operation window (=Vtwrite−Vterase) is gradually decreased, as shown in FIG. 5.